μ PD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
Feature Differences between QDR II and QDR II+
Features
Frequency (DLL/PLL ON)
Organization
V DD
V DD Q
Read Latency
Write Latency
Input Clocks (K, K#)
Output Clocks (C, C#)
Echo Clock Number (CQ, CQ#)
Package
Individual Byte Write (BWx#)
QVLD
ODT
QDR II
200 MHz to 333 MHz
x9 / x18 / x36
1.8 ± 0.1 V
1.8 ± 0.1 V or 1.5 ± 0.1 V
1.5 clock cycles
1.0 clock cycle
Single Ended (K, K#)
Yes
1 Pair
165-pin PLASTIC BGA (15 x 17)
Yes
No
No
QDR II+
300 MHz to 500 MHz
x9 / x18 / x36
1.8 ± 0.1 V
1.8 ± 0.1 V or 1.5 ± 0.1 V
2.0 & 2.5 clock cycles
1.0 clock cycle
Single Ended (K, K#)
No
1 Pair
165-pin PLASTIC BGA (15 x 17)
Yes
Yes
Yes
Note
1
2
3
4
5
Notes 1. QDR II+ read latency is not user selectable. Offered as two different devices. 2.5 clock cycle is consortium
standard, and 2.0 clock cycle is vendor option.
2. QDR II+ write latency is 1.0 clock cycle regardless of read latency.
3. Echo Clocks are single-ended outputs.
4. Edge aligned with Echo Clocks
5. ODT ON/OFF is user selectable.
Data Sheet M19962EJ2V0DS
3
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